Verilog较好的一篇教程.pptVIP

Verilog Matt Tsai Verilog Application Introduction to Cadence Simulators Sample Design Lexical Conventions in Verilog Verilog Data Type and Logic System Structural Modeling Modeling Delay Using Compiler Controls Verilog Operators Behavioral Modeling Support for Verification Introduction to Using a Verilog Test Bench Modeling Memories High Level Constructs in Verilog User Defined Primitives Annotating SDF Timing IEEE 1364-1995, IEEE 1364-2001 Behavioral: 無法看出電路特性 RTL:可以看出電路特性 (logic synthesis) Structural: bulit-in primitives,UDPs RTL and structural 可混合描述 Behavioral 和 RTL的區分要靠經驗 Compilation(1)