ScalableLoadandStoreProcessinginLatencyTolerant.pptVIP

Scalable Load and Store Processing in Latency Tolerant Processors Amit Gandhi1,2 Haitham Akkary1 Ravi Rajwar1 Srikanth T. Srinivasan1 Konrad Lai1 1Intel 2Portland State University Problem: tolerating miss latencies Increasing miss latencies to memory large instruction windows tolerate latencies na?ve window scaling impractical Resource efficient large instruction windows sustain 1000s of instructions in-flight need small register files and schedulers do not address memory buffers efficiency Why is this a problem? Memory operations tracked in load store buffers buffers require CAMs for scann