超大CMOS集成电路原理chapter10.pptVIP

EE141 EE141 Digital Integrated CircuitsA Design Perspective Synchronous Timing Timing Definitions Latch Parameters Register Parameters Clock Uncertainties Clock Nonidealities Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, tSK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS Long term tJL Variation of the pulse width Important for level sensitive clocking Clock Skew and Jitter Both skew and jitter affect the effective cycle time Only skew affects the race margin Clock Skew Positive and Negative Skew Positive Skew Negative Skew Timing Constraints Timing Constraints Impact of Jitter Longest Logic Path in Edge-Triggered Systems Clock Constraints in Edge-Triggered Systems Shortest Path Clock Constraints in Edge-Triggered Systems How to counter Clock Skew? Flip-Flop – Based Timing Flip-Flops and Dynamic Logic Latch timing Single-Phase Clock with Latches Latch-Based Design Slack-borrowing Latch-Based Timing Clock Distribution More realistic H-tree The Grid System Example: DEC Alpha 21164 21164 Clocking 2 phase single wire clock, distributed globally 2 distributed driver channels Reduced RC delay/skew Improved thermal distribution 3.75nF clock load 58 cm final driver width Local inverters for latching Conditional clocks in caches to reduce power More complex race checking Device variation Clock Skew in Alpha Processor 2 Phase, with multiple conditional buffered clocks 2.8 nF clock load 40 cm final driver width Local clocks can be gated “off” to save power Reduced load/skew Reduced thermal issues Multiple clocks complicate race checking 21264 Clocking EV6 Clock Results EV7 Clock Hierarchy Self-timed and Asynchronous Design Synchronous Pipelined Datapath Self-Timed Pipelined Datapath Completion Signal Generation Completion Signal Generation Completion Signal in DCVSL Self-Timed Adder Completion Signal Using Current Sensing Hand-Shaking Protocol