DSP 2335 教程 7.pptVIP

DSP24 12 Analog-to-Digital Converter Module 6 TMS320C28x? MCU Workshop Learning Objectives Understand the operation of the Analog-to-Digital converter (ADC) Use the ADC to perform data acquisition ADC Module Block Diagram (Cascaded Mode) ADC Module Block Diagram (Dual-Sequencer mode) ADC Operating Mode Choices The user can make one choice from each category below Choices are completely independent * ADC Clocking Flow Analog-to-Digital Converter RegistersAdcRegs.register (lab file: Adc.c) ADC Control Register 1AdcRegs.ADCTRL1 ADC Control Register 1AdcRegs.ADCTRL1 ADC Control Register 2AdcRegs.ADCTRL2 ADC Control Register 2AdcRegs.ADCTRL2 ADC Control Register 3AdcRegs.ADCTRL3 Maximum Conversion Channels RegisterAdcRegs.ADCMAXCONV ADC Input Channel Select Sequencing Control RegistersAdcRegs.ADCCHSELSEQx Example - Sequencer Configuration (1 of 2) Configuration Requirements: ePWM triggers the ADC Three autoconversions (V1, V2, V3) off trigger 1 (CTR = 0) Three autoconversions (I1, I2, I3) off trigger 2 (CTR = PRD) ADC in cascaded sequencer and sequential sampling modes Example - Sequencer Configuration (2 of 2) MAX_CONV1 is set to 2 and Channel Select Sequencing Control Registers are set to: Once reset and initialized, SEQ1 waits for a trigger First trigger, three conversions performed: CONV00 (V1), CONV01 (V2), CONV02 (V3) MAX_CONV1 value is reset to 2 (unless changed by software) SEQ1 waits for second trigger Second trigger, three conversions performed: CONV03 (I1), CONV04 (I2), CONV05 (I3) End of second sequence, ADC Results registers have the following values: SEQ1 waits at current state for another trigger User can reset SEQ1 by software to state CONV00 and repeat same trigger 1,2 session ADC Conversion Result Registers How Can We Handle Signed Input Voltages? Built-In ADC Calibration TI reserved OTP contains device specific ADC calibration data (2 words) The Boot ROM contains an ADC_cal() routine (6 words) that copies the