第八章 动态逻辑电路课题.pptVIP

西安理工大学 微电子学硕士课程 第8章 动态逻辑电路 动态四输入与非门 四、动态逻辑电路存在的问题-1:电荷泄漏 泄漏电荷的影响 电荷泄漏的解决方法 解决方法:对中间节点也进行预充电 时钟馈通 动态逻辑门的级联问题 多米诺逻辑 为什么称做多米诺? np-CMOS (Zipper) 如何选择逻辑方式 设计的简易程度，鲁棒性，面积，速度，功耗 作业： CLK CLK Me Mp A B Out Mkp CLK CL CLK CLK B A Out Mp Me 四、动态逻辑电路存在的问题-3:时钟馈通 CLK CLK In1 In2 In3 In4 Out In CLK Out Time, ns Voltage 时钟馈通 Clock feedthrough Clock feedthrough CL CLK CLK Out1 In Mp Me Mp Me CLK CLK Out2 V t CLK In Out1 Out2 ?V 在评估阶段，只允许有 0 ? 1的跳变! In1 In2 PDN In3 Me Mp CLK CLK Out1 In4 PDN In5 Me Mp CLK CLK Out2 Mkp 1 ? 1 1 ? 0 0 ? 0 0 ? 1 In1 CLK CLK Ini PDN Inj Ini Inj PDN Ini PDN Inj Ini PDN Inj 跳变象多米诺骨牌! In1 In2 PDN In3 Me Mp CLK CLK Out1 In4 PUN In5 Me Mp !CLK !CLK Out2 (to PDN) 1 ? 1 1 ? 0 0 ? 0 0 ? 1 在评估阶段： 对PDN网只允许有 0 ? 1 跳变 对 PUN网只允许 有 1 ? 0 跳变 to other PDN’s to other PUN’s 动态逻辑电路对实现快速、小的复合门方面具有优势，但具有电荷泄漏、电荷分配等效应，设计时需考虑。 静态互补CMOS组合逻辑电路具有好的噪声容限，完善的自动化设计工具，因此是最好的通用型逻辑设计方式。但对于大扇入的复合逻辑门会导致面积和性能的退化。 传输门逻辑在一些如：多路选择器，以异或门为主的逻辑（如加法器）等特定的电路中具有明显的优势。 * * * * leakage sources are reverse-biased diode (1) and the sub-threshold leakage (2) of the NMOS pulldown device. Charge stored on CL will leak away with time (input in low state during evaluation) Requires a minimum clock rate - so not good for low performance products such as watches (or when have conditional clocks) PMOS precharge device also contributes some leakage due to reverse bias diode (3) and subthreshold conduction (4) that, to some extent, offsets the leakage due to the pull down paths. During precharge, Out is VDD and inverter out is GND, so keeper is on During evaluation if PDN is off, the keeper compensates for drained charge due to leakage. If PDN is on, there is a fight between the PDN and the PUN - circuit is ratioed so PDN wins, eventually Note Psc during switching period when PDN and keeper are both on simultaneously CA initially discharged and CL fully charged. Danger is that signal levels can rise enough above VDD that the normally reverse-biased junction diodes become forward-biased causing electrons