数字电路与逻辑设计_2013_12.pptVIP

例一：四位二进制数转换为BCD码。 entity bcd2b is port(d:in std_logic_vector(3 downto 0); Bh,Bl:out std_logic_vector(3 downto 0)); end bcd2b; architecture aa of bcd2b is signal a,b:std_logic_vector(7 downto 0); begin a = 0000d; b = a when d10 else a+6; Bh = b(7 downto 4); Bl = b(3 downto 0); end aa; architecture ab of bcd2b is begin Bh = 0001 when d9 else 0000; Bl = d+6 when d9 else d; end ab; 例二：设计一位BCD码加法器 entity bcd_adder is port(d1,d2:in std_logic_vector(3 downto 0); Bh,Bl:out std_logic_vector(3 downto 0)); end bcd_adder; architecture aa of bcd_adder is signal a,b,t,s:std_logic_vector(7 do