Cellular Phones as Embedded Systems University of 蜂窝电话作为嵌入式系统大学.ppt

* of 23 * of 33 * of 33 Pipelines for Future Architectures in Time Critical Embedded SystemsBy: R.Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, and C.Ferdinand EEL 6935 - Embedded Systems Dept. of Electrical and Computer Engineering University of Florida Liza Rodriguez Aurelio Morales Outline Pipelining Review Timing Analysis Anomalies Domino Effects Architecture Classifications Conclusions Outline Pipelining Review Timing Analysis Anomalies Domino Effects Architecture Classifications Conclusions Pipelining Review Pipelining is an implementation technique where multiple instructions are overlapped in execution Pipelining takes advantage of parallelism that exists among the actions needed to execute and instruction Pipelining is like an assembly line, each stage operates in parallel with the other stages Instructions enter at one end, progress through the stages, and exit at the other end Pipelining is the key implementation technique used to make fast CPUs Pipelined Example LD r4, 0(r3) Fetch Decode Execute Memory Write Back LD r4, 0(r3) 5 cycles (5) ADD r1, r7, r3 1 cycles (4) ADD r1, r7, r3 001100 r4 LOAD 0 + r3 read LD r4, 0(r3) ADD r1, r7, r3 101011 ADD r7 + r3 ADD r2, r6, r30 101011 ADD r6 + r3 ADD r2, r6, r30 ADD r2, r6, r30 1 cycles (4) XXX XXX r1 r2 Pipeline registers separate functional units to allow parallel operation Pipeline will stall if there is a hazard Further Optimizations Superscalar – executes more than one instruction per clock cycle by simultaneously dispatching multiple instructions to redundant functional units Branch Prediction – predict branches based on a predefined static algorithm or based on dynamic branch history Out of order execution – instructions are dynamically scheduled to avoid hazards and dependencies that may stall the pipeline Fetch Decode Execute Memory Write Back Fetch Decode Execute Memory Write Back Execute ADD r1, r2, r3 wait SUB r1, r2, r3 wait MUL r