Combinational Logic Department of Computer Science组合逻辑计算机科学系.ppt

Combinational Logic Multi-input gates - (x+(y*z))’ Half Adder 1-bit addition (x + y) outputs: sum s and carry c s = xy’ + x’y (x XOR y or x ? y) c = xy Full 1-bit adder Need a carry in ci CMOS adder Multiplexor A multiplexor (selector or mux) selects one of n inputs to be output Let’s make it easy and start with a 2-input mux when s = 0, f = a when s = 1, f = b 2 input Multiplexor design Making bigger muxes You can design them directly, or just glue together smaller muxes: Decoders Decode an n-bit input to set output line 2n-1 Programmable Logic Array (PLA) Since all Boolean functions can be expressed in sum of products form, we can implement a set of n input functions systematically in hardware using a PLA University of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell * University of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell y x Out Vdd z 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 1 0 0 0 x 0 1 1 1 0 1 1 0 z 1 0 1 0 out y Very easy with inverting gates 1 0 0 0 c 0 1 1 1 0 1 1 0 y 1 0 0 0 s x x y s c 1 0 1 1 0 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 0 0 x 1 0 0 0 co 1 1 1 1 0 1 1 0 ci 1 0 0 0 s y s = x’yci’+ xy’ci’ + x’y’ci + xyci = ci’(x’y+xy’) + ci (xy+x’y’) = ci’(x’y+xy’) + ci (x’y+xy’)’ = ci ? (x ? y) co = x’yci + xy’ci + xyci’ + xyci = ci (x’y+xy’) + xy(ci’+ci ) = ci (x ? y) + xy x y s ci co For the carry, we can first use De Morgan’s laws For the xor, recall that a xor b = ab’ + a’b and (a xor b)’ = ab + a’b’ Vdd x’ y Out x y’ y x’ x y’ x y s ci co co x y s ci a b c d f s0 s1 a b f s 1 1 1 0 0 0 0 1 1 1 0 1 0 0 1 1 1 0 0 0 s 1 1 1 1 0 1 1 0 b 0 0 0 0 f a f = s’ab’ + s’ab + sa’b + sab = s’a(b’+b) + sb(a’+a) = s’a + sb b a s f c d f s1 a b s0 a b 11 10 01 00 1 0 0 0 11 0 1 0 0 10 0 0 1 0 01 0 1 1 0 0 1 1 0 b 0 0 1 0 00 a 00 01 10 11 b a b a Connections f2 f1 f0 University of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell