Comparing FPGA vsFPGA与比较. Custom CMOS and the Impact on Processor.pptVIP

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Comparing FPGA vsFPGA与比较. Custom CMOS and the Impact on Processor.ppt

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* Comparing FPGA vs. Custom CMOS and the Impact on Processor Microarchitecture Henry Wong Vaughn Betz, Jonathan Rose Processor Microarchitecture Microarchitecture: How to arrange circuits to make a processor Depends on how efficient the circuits are Which depends on the substrate Custom CMOS Standard Cell FPGA Goals Make good microarchitecture design choices for bigger and faster FPGA soft processors Much existing literature on processor design for custom CMOS implementation Comparisons of overall area/delay between substrates exist But relative building block costs vary up to two orders of magnitude on FPGA vs. Custom CMOS This work: compares building blocks and infer microarchitectural conclusions Also applicable to circuits other than processors What were measuring Focus on processors as the complete circuit FPGA vs. Custom: Synthesize RTL for FGPA Compare building block circuits that are often used in processors SRAM, CAM, Multiplier, Adder, … Infer how existing microarchitectures should be modified for FPGA Methodology FPGA circuits synthesized through Quartus II 10.0 Largest, fast speed grade, 65 nm Stratix III (3LS340) Area calculated from FPGA tile areas A few results are from literature Custom CMOS design examples found in literature High-performance circuit design and layout are difficult and time consuming Normalize to 65 nm: Ideal area scaling and ring oscillator delay scaling Metrics Area Still a key design constraint on FPGAs Delay Power or energy: Not considered here Data not often published and testing conditions not standard. FPGA users mostly spared responsibility for not melting the chip. 1. Processor Core Comparison Complete circuit serves as a reference point for sub-circuit measurements later Processor Core Comparison SPARC T1 and T2, Intel Atom and Nehalem Compare CMOS to FPGA implementations Compare just one core, excludes large caches FPGA implementation used RTL optimized from the custom CMOS implementation Atom and Nehalem results