5-中断技术-7.3..ppt

The ICR can be used for the following functions: ?To send an interrupt to another processor. ?To allow a processor to forward an interrupt that it received but did not service to another processor for servicing. ?To direct the processor to interrupt itself (perform a self interrupt). ?To deliver special IPIs, such as the start-up IPI (SIPI) message, to other processors. * Figure 9-17. Interrupt Command Register (ICR)310Reserved7VectorDestination Shorthand810Delivery Mode000: Fixed001: Lowest Priority100: No Shorthand01: Self11121314151617181910: All Including Self11: All Excluding Self010: SMI011: Reserved100: NMI101: INIT110: Start Up111: ReservedDestination Mode0: Physical1: LogicalDelivery Status0: Idle1: Send PendingLevel0 = De-assert1 = AssertTrigger Mode0: Edge1: Level6332ReservedDestination Field56Address: FEE0 0300H (0 - 31)Value after Reset: 0HReserved2055FEE0 0310H (32 - 63) NOTE:1. The ability of a processor to send Lowest Priority IPI is model specific. Delivery Mode Specifies the type of IPI to be sent. This field is also know as the IPI message type field. 000 (Fixed)Delivers the interrupt specified in the vector field to the target processor or processors. 001 (Lowest Priority)Same as fixed mode, except that the interrupt is delivered to the processor executing at the lowest priority among the set of processors specified in the destination field. The 9-40 Vol. 3 ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC) ability for a processor to send a lowest priority IPI is model specific and should be avoided by BIOS and operating system software. 010 (SMI)Delivers an SMI interrupt to the target processor or processors. The vector field must be programmed to 00H for future compatibility. 011 (Reserved) 100 (NMI)Delivers an NMI interrupt to the target processor or processors. The vector information is ignored. 101 (INIT)Delivers an INIT request to the target processor or processors, which causes them to perform an INIT. As a result of this IPI mes