《1并行语句程序演示.docVIP

常见的并行语句有： 进程语句 块语句 并行信号赋值语句 并行过程调用语句 元件例化语句 生成语句 并行断言语句 1、进程语句举例 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY d_ff IS PORT( clk, d: IN STD_LOGIC; q: OUT STD_LOGIC); END d_ff; ARCHITECTURE my_arch OF d_ff IS BEGIN PROCESS(clk) BEGIN IF clk EVENT AND clk = 1 THEN q = d; END IF; END PROCESS; END my_arch; 2、块语句举例 多个BLOCK ENTITY cpu IS PORT (clk, interrupt : IN STD_LOGIC; addr : OUT tw32;　 data : INOUT tw32); END cpu; ARCHITECTURE cpu_blk OF cpu IS SIGNAL ibus, dbus : tw32; BEGIN ALU: BLOCK SIGNAL qbus : tw32; BEGIN …… -- 并行处理语句 END BLOCK ALU; REG8: BLOCK SIGNAL zbus: tw32; BEGIN …… -- 并行处理语句 END BLOCK REG8; END cpu_blk; 嵌套BLOCK b1: BLOCK SIGNAL s: BIT; --BLOCK b1中s的说明 BEGIN s = a AND b; --s来自b1 b2: BLOCK SIGNAL s1: BIT; --BLOCK b2中s1的说明 BEGIN s1 = c AND d; --s1来自b2 b3: BLOCK BEGIN z = s; --s来自b1 END BLOCK b3; END BLOCK b2; y = s; --s来自b1 END BLOCK b1; 3、条件信号赋值语句应用举例 四选一数据选择器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4 IS PORT (i0, i1, i2, i3, a, b: IN STD_LOGIC; q : OUT STD_LOGIC); END mux4; ARCHITECTURE arch1 OF mux4 IS SIGANL sel : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN sel = a b; q = i0 WHEN sel = 00 ELSE i1 WHEN sel = 01 ELSE i2 WHEN sel = 10 ELSE i3 WHEN sel = 11 ELSE X; END arch1; 4、选择信号赋值语句应用举例 四选一数据选择器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4 IS PORT (i0, i1, i2, i3, a, b: IN STD_LOGIC; q: OUT STD_LOGIC); END mux4; ARCHITECTURE arch2 OF mux4 IS SIGANL sel : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN sel = a b; WITH sel SELECT