《数字电压表VHDL程序.docxVIP

数字电压表 数字电压表设计 简易数字电压表 数字电压表的设计 单片机数字电压表 数字电压表的发展 数字电压表发展 数字电压表原理 数字电压表 论文程序如下：LIBRARY ieee; --A/D0809use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity ad is port(ST,eoc:in std_logic; --控制端口d:in std_logic_vector(7 downto 0);oe,sta,ale,adda:out std_logic;q:out std_logic_vector(7 downto 0));end ad;architecture a of ad istype states is(st0,st1,st2,st3,st4,st5,st6); --7个状态signal c_state,n_state:states :=st0;signal regl:std_logic_vector(7 downto 0);signal lock:std_logic;begin adda=1;com:process(c_state,eoc)begincase c_state iswhen st0=ale=0;sta=0;oe=0;lock=0;n_state=st1;when st1=ale=1;sta=0;oe=0;lock=0;n_state=st2;when st2=ale=0;sta=1;oe=0;lock=0;n_state=st3;when st3=ale=0;sta=0;oe=0;lock=0;if(eoc=1) then n_state=st4;else n_state=st3; ――eoc为‘1’转换结束 进入下一状态end if; ――否则 继续转换when st4=ale=0;sta=0;oe=1;lock=0;n_state=st5;when st5=ale=0;sta=0;oe=0;lock=1;n_state=st6;when st6=ale=0;sta=0;oe=0;lock=1;n_state=st0;when others=n_state=st0;end case;end process com;reg:process(st) beginif(stevent and st=1) thenc_state=n_state;end if;end process reg;lo:process(lock) --锁存begin if(lockevent and lock=1) then regl=d;end if;end process lo;q=regl; end a;――BCD 8位转12LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY BCD ISPORT (V:IN STD_LOGIC_VECTOR(7 DOWNTO 0);HB,LB:BUFFER STD_LOGIC_VECTOR(11 DOWNTO 0);BVALUE:BUFFER STD_LOGIC_VECTOR(11 DOWNTO 0);BCD_L,BCD_M,BCD_H:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END BCD;ARCHITECTURE A OF BCD ISBEGINP1:PROCESS(V(7 DOWNTO 4)) BEGIN --A/D输出高4位转换 分辨率0.32VIF V(7 DOWNTO 4)=1111 THEN HB=010010000000; --4.80VELSIF V(7 DOWNTO 4)= 1110 THEN HB=010001001000;--4.48VELSIF V(7 DOWNTO 4)= 1101 THEN HB=010000010110;--4.16VELSIF V(7 DOWNTO 4)= 1100 THEN HB=001110000100;--3.84VELSIF V(7 DOWNTO 4)= 1011 THEN HB=001101010010;--3.52VELSIF V(7 DOWNTO 4)= 1010 THEN HB=001100100000;--3.20VELSIF V(7 DOWNTO 4)= 1001 THEN HB=001010001000;--2.88VELSIF V(7 DOWNTO 4)= 1000 THEN HB=00100