[eda程序.docVIP

跑马灯； library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity paomadeng is port(clk : in std_logic; input: in std_logic; reset: in std_logic; q: out std_logic_vector(7 downto 0)); end; architecture rtl of paomadeng is type state_type is (s0, s1, s2, s3); signal state : state_type; signal q1:std_logic_vector(7 downto 0); signal count:std_logic_vector(3 downto 0); begin process (clk, reset) begin if reset = 1 then state = s0; q1=(others=0); elsif (rising_edge(clk)) then case state is when s0= if q1then --s0 q1