ICC wo的rk shop Data_Setup.pptxVIP

Agenda ? 2010 Synopsys, Inc. All Rights Reserved Synopsys 20-I-071-SSG-010 Unit Objectives After completing this unit, you should be able to: Perform data setup to create an initial design cell which is ready for design planning: Load necessary synthesis data: logical libraries, constraints, netlist Load necessary physical design data: physical libraries, technology file, RC parasitic model files Create a Milkyway design library and initial design cell Apply timing and optimization controls Perform checks on libraries, RC parasitic models, constraints and timing Execute a basic flow which includes loading a floorplan and performing placement, CTS and routing A Word of Caution About Scripts and Flows This workshop contains many scripts and flow diagrams showing specific commands executed in a specific order These flows DO NOT represent“the recommended flow” Each flow is just one exampleof many possible flows They help to better organize andpresent the material The specific commands and order of execution required to achieve the best results is completely design dependent There is no “golden script” for physical design General IC Compiler Flow Synthesis Data Setup Design Planning Placement Clock Tree Synthesis Routing Chip Finishing This Unit Data Setup Placed, Routed Optimized Layout with Clock Trees ICCompiler MW Standard cells MW Macro cells MW Pad cells Logical Libraries Provide timing and functionality information for all standard cells (and, or, flipflop, …) Provide timing information for hard macros(IP, ROM, RAM, …) Define drive/load design rules: Max fanout Max transition Max/Min capacitance Are usually the same ones used by Design Compiler during synthesis Are specified with variables: target_library link_library Physical Reference Libraries Contain physical informationof standard, macro and pad cells, necessary for placementand routing Define placement unit tile Height of placement rows Minimum width resolution Preferred routing directions Pitch