FIRFilter培训讲义.ppt

3-Tap FIR Filter Optimizations By: Jeff Rybczynski CMPE 222 3-Tap FIR Filter Design FIR Filter Control Six States meaning 3 bit State Variable Each Multiply is in a separate state Asynchronous Reset FIR Filter Data Path 3 Independent Multiply Operations 3 Independent Addition Operations Not order dependent Optimized FIR Control Take out extra calculate steps and place all the multiplies in one CALC state Add the values from the multiply step together in ADD state Place value directly into result before you raise output_ready Changes to the Verilog Code Changes to the Verilog Code Array Multiplier Similar to how you multiply by hand Cascading Array multiplier blocks Array Multiplier Block Array Multiplier Add Array Multiplier to Verilog Code New Code: FIR Designs *FIR Optimization – Jeff Rybczynski * 3b100 : begin output_ready = 1b0; rin = sample; end 3b110 : acc = rin * 24h702a78; 3b111 : acc = rs0 * 24h800000 + acc; 3b101 : acc = rs1 * 24h4fd547 + acc; 3b001 : begin output_ready = 1b1; result = acc; rs1 = rs0; rs0 = rin; end default : begin acc = 24h000000; output_ready = 1b0; end Original Verilog Code Optimized Code 2b00 : begin output_ready = 1b0; rin = sample; end 2b10 : begin temp1 = rin * 24h702a78; temp2 = rs0 * 24h800000; temp3 = rs1 * 24h4fd547; end 2b11 : begin result = temp1 + temp2 + temp3; rs1 = rs0; rs0 =rin; output_ready =1’b1 end 2b01 : output_ready = 1b0; 6x6 Multiplier 0 A B CO CI S????? A B CO CI S????? A B CO CI S????? A B CO CI S????? A B CO CI S????? A B CO CI S????? A B CO CI S????? A B CO CI S????? A B CO CI S????? A B CO CI S????? A B CO CI S????? A B CO CI S????? A B CO CI S????? A B CO CI S????? A B CO CI S????? A B CO CI S????? 0 0 0 0 0 0 0 A3=1 A2=0 A1=1 A0=1 B0=1 B1=0 B2=1 B3=1 1 0 1 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 1 0 1 1 0 1 0 0 1 0 A B CO CI S????? A B CO CI S????? A B CO C