Verilog, Pipelined ProcessorsCPSC 培训教程文件.pptVIP

Verilog, Pipelined ProcessorsCPSC 321 Andreas Klappenecker Today’s Menu Verilog Pipelined Processor Recall: n-bit Ripple Carry Adder module ripple(cin, X, Y, S, cout); parameter n = 4; input cin; input [n-1:0] X, Y; output [n-1:0] S; output cout; reg [n-1:0] S; reg [n:0] C; reg cout; integer k; Recall: ‘=’ versus ‘=’ initial begin a=1; b=2; c=3; x=4; #5 a = b+c; // wait 5 units, grab b,c, // compute a=b+c=2+3 d = a; // d = 5 = b+c at time t=5. x = #6 b+c; // grab b+c now at t=5, don’t stop // assign