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滨江学院 题 目 专 业姓名 学 号 二Ｏ一三 年 月 日II，进行逻辑功能仿真与时序验证，并在FPGA开发板上进行了综合和适配。 关键词：计数器；HDL；集成电路设计；仿真 ABSTRACT A precise calculargraph is usually applied to any technical fields as athletic competition that demands accuratetiming. Usually, the design of precise calculargraph can be maded by using mediate scale integrate circuit. The study which is based on the new hardware description language and adapts the design method of ASIC will realize the advanced design of calculargraph whose accuracy will be 1/100s. This calculargraph, including keyin module, clock frequency division module, switching and controlling module, display module ,can realize the function exercised by accurate calculargraph of 1/100s . The key_in module will produce reset0 and on_off0. Clock frequency division is actually a frequency division circuit divided by a calculator. When divided 10 times 1 KHz clock signal will result in clock’s 100Hz clock pulse signal and redivided 4 times it will result in 25Hz. The controlling sub_module is used to control whether enable the calculating signal according to the calculator’s working status. The calculating sub_module is a calculating timer, used to display 8_figure calculating information when the enable signal starts calculating effectively. The input signal of calculargraph display module is the calculating information it outputs, with the output signal choose and segment, driving the eight LED 7_section display digital tube used for calculating display. When it outputs signals, the LED 7_section display digital tube will be highlighted in circles to display the calculating output because of the 8_figure display’s calculating in circles. When describing all function modules’ hardwares, a programming software plat from Quartus II will be developed. Its logical function emulation and time sequence will be tested, integrated into specific device and adapted. Key words： calculargraph; HDL; integrate