8-2Edge-TriggeredFlip-Flops边缘触发正反器.ppt

8-1 Latches 栓鎖電路 Active High, Active Low S-R Latch Contact Bounce Gated S-R Latch Gated D Latch Figure 8--1 Two versions of SET-RESET (S-R) latches. Open file F08-01 and verify the operation of both latches. Figure 8--2 Negative-OR equivalent of the NAND gate S-R latch in Figure 8-1(b). Figure 8--3 The three modes of basic S-R latch operation (SET, RESET, no-change) and the invalid condition. Figure 8--4 Logic symbols for the S-R and S-R latch. Figure 8--5 Figure 8--6 The S-R latch used to eliminate switch contact bounce. Figure A--13 The 74LS279 quad S-R latch. Figure 8--7 A gated S-R latch. Figure 8--8 Figure 8--9 A gated D latch. Figure 8--10 Figure A--14 The 74LS75 quad gated D latches. Figure 8--11 Edge-triggered flip-flop logic symbols (top: positive edge-triggered; bottom: negative edge-triggered). 8-2 Edge-Triggered Flip-Flops 邊緣觸發正反器 正緣觸發, 負緣觸發 邊緣觸發脈波產生器 邊緣觸發S-R正反器 邊緣觸發D型正反器 邊緣觸發J-K正反器 具有非同步的Preset及Clear端之J-K正反器 Figure 8--12 Operation of a positive edge-triggered S-R flip-flop. Figure 8--13 Figure 8--15 Edge triggering. Figure 8--16 Flip-flop making a transition from the RESET state to the SET state on the positive-going edge of the clock pulse. Figure 8--17 Flip-flop making a transition from the SET state to the RESET state on the positive-going edge of the clock pulse. Figure 8--18 A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter. Figure 8--19 Figure 8--20 A simplified logic diagram for a positive edge-triggered J-K flip-flop. Figure 8--21 Transitions illustrating the toggle operation when J =1 and K = 1. Figure 8--22 Figure 8--23 Figure 8--24 Logic symbol for a J-K flip-flop with active-LOW preset and clear inputs. Figure 8--25 Logic diagram for a basic J-K flip-flop with active-LOW preset and clear inputs. Figure 8--26 Open file F08-28 to verify the operation. Figure A--15 Logic symbols for the 74AHC74 dual positive edge