数字设计基础双语教学版作者英BarryWilknson双语课件（第10章）课案.pptVIP

* 10. Behavioral and Structural Descriptions 10.1 An example 10.2 The dataflow description 10.3 Structural VHDL 10.4 Processes 10.5 Sequential and concurrent VHDL 10.1 An example Example: a Four-bit adder sum = x + y; Describe a 4-bit adder in VHDL 1 1 1 1 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 Carry out Sum Carry in y x 10.1 An example Circuit diagram 10.2 The dataflow description a behavioral description of the full adder LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY fulladd IS PORT ( x, y, cin: IN STD_LOGIC; sum,