数字设计基础双语教学版作者英BarryWilknson双语课件（第11章）课案.pptVIP

* 11. VHDL simulation 11.1 Simulation 11.2 VHDL simulation of dataflow code 11.3 Simulation of structural VHDL 11.4 The uninitialized logic value 11.5 Delay modeling 11.6 Test benches 11.1 Simulation VHDL descriptions must be simulated to confirm that they behave as required. Simulation allows us to apply inputs, and then trace how the rest of the circuit evolves with time as the influence of the new inputs propagates through towards the outputs. We can then compare the predicted outputs for our design to the desired outputs. If there are no differences then we can conclude tha