C55x典型应用系统设计20161206.ppt.ppt

EMIF_config函数的定义(续): #if (CHIP_5509A) { Uint16 clkMem = Config-egcr _EMIF_EGCR_MEMFREQ_MASK; Uint16 mMask = _EMIF_CE01_MTYPE_MASK; Uint16 mSdram = ((Config-ce01 mMask) != 0) || ((Config-ce11 mMask) != 0) || ((Config-ce21 mMask) != 0) || ((Config-ce31 mMask) != 0); if (clkMem mSdram) { _EMIF_IPMR = 0x0000u; } } #endif IRQ_globalRestore(oldgie); } * MEMFREQ: 是egcr的8-10位, 即大于等于001b(频率小于等于CPU时钟的1/2分频), 即CLKMEM频率不是CPU时钟(000b), 而是CPU时钟的各分频(1/2, 1/4, 1/8, 1/16分频 ) 即CE01的MTYPE值 _EMIF_IPMR: Internal Power Management Register #define _EMIF_IPMR_ADDR (0x0814u) #define _EMIF_IPMR PREG16(_EMIF_IPMR_ADDR) #define _IPMR _EMIF_IPMR On the TMS320VC5509A devices, there is an SDRAM control register 3 containing a DIV1 bit. If MEMFREQ = 000b (divide-by-1 clock mode), this register must contain 0007h (DIV1=1). For other values of MEMFREQ, this register must contain 0003h(DIV1=0). 最低两位要求总是11b。 On the TMS320VC5509 devices, the external bus selection register (EBSR) contains an EMIFX2 bit (see the data manual). If the CPU is programmed to operate at 144 MHz and MEMFREQ = 001b(divide-by-two), the EMIFX2 bit must be 1 in the external bus selection register (EBSR) of the DSP. For other MEMFREQ values, the EMIFX2 bit must be 0. This is required for proper timing of SDRAM accesses. 应该是5509A的SDRAM Control Register 3 (SDC3) /*恢复全局中断屏蔽位INTM的原状态值*/ 意思是若用SDRAM且其频率不是CPU时钟MEMFREQ 不等于= 000b SDRAM的EMIF设置例子: /* This is an example for EMIF of C5509? ---------------------? ?*/#include csl.h#include csl_pll.h#include csl_emif.h#include csl_chip.h/* Uint16 x; *//* Uint32 y; */CSLBool b;unsigned int datacount = 0;int databuffer[1000] ={0};int *souraddr,*deminaddr;/*锁相环的设置*/PLL_Config??myConfig?= {??0,? ? //IAI: the PLL locks using the same process that was underway?? ?? ?? //before the idle mode was entered??1,? ? //IOB: If the PLL indicates a break in the phase lock,?? ??