标题二号，黑体，英文字体为黑体，1-电子技术应用.doc

高速HART C8PSK位同步与均衡系统设计 金郑华1 2　王宏1　杨志家1 (1中国科学院沈阳自动化研究所工业信息学重点实验室， 沈阳110016; 2中国科学院研究生院，北京 100039 ) 摘　要：HART 基金会主导研制的第二代HART C8PSK接收机因功耗过大未在生产中使用。本文提出一种新的低功耗HART C8PSK位同步与均衡结构，其中位同步初始化使位同步快速稳定，减少位同步跟踪计算频率和所需信号采样，从而降低均衡器和插值器的计算频率。同时根据HART信道特点，提出一种新的基于CSD编码的均衡器结构，使每个采样点均衡运算功耗大幅降低。整个系统通过资源复用，大量节省硬件资源。通过分析和仿真表明，该结构不仅能大幅降低功耗，而且具有很好的抗噪声性能。 关键字：高速HART 位同步　CSD编码预置式均衡器　信道估计 分类号：TP393 The Timing and Equalizer Structure Design of High Speed Hart C8PSK Jin Zhenghua1 2 Wang Hong2 Yang Zhijia2 （1Graduate School of the Chinese Academy of Sciences, Beijing 10039; 2 Shenyang Institute of Automation Chinese Academy of Sciences Liaoning Shenyang 110016） Abstract: Due to high power consumption, the high speed HART C8PSK receiver designed by HART Communication Foundation had not been applied in practice. This paper presents a novel low power HART C8PSK timing and equalization structure. The timing synchronizer attains equilibrium state quickly by using timing initialization, and subsequently reduces work frequency and samples needed for the timing tracking. So interpolator and equalizer, which offer samples for synchronizer, can work in low frequency too. According to the characteristic of HART channel, a novel CSD coded preset equalizer structure is introduced to lower the power consumption of equalizer operation for one sample. The whole structure saves resources by reusing them. Analysis and simulation has shown that the structure we developed not only can reduce power consumption but also has good noise tolerance. Key words: High Speed HART, timing, CSD coded preset equalizer, channel estimation 1 引言 HART(Highway Addressable Remote Transducer)，在已有低频4-20mA模拟信号上叠加小幅的数字通讯信号，进行双向数字通讯，是全球最重要的现场仪表总线协议之一，目前为止仍使用1985制定HART FSK第一代协议（Bell-202标准）。2001年HART基金会制定第二代协议,规定高速HART（High Speed Hart, HSH）使用C8PSK（ITU V2.7标准）传输数字信号，可将现有数字通讯速度理论上提高８倍，考虑数据帧结构的改进，实际数字通讯速度可提高11.6倍[1]。 第二代HART 协议制定同时，由HART基金会组织，Rosemont、Siemens和ABB等工业巨头联合开发了HSH接收机，由于当时全数字接收机理论水平和半导体工艺限制，研制的HSH接收机功耗高达1.5mA，超过了HART 协议规