MultiValued Logic Synthesis EECS at UC Berkeley多值逻辑合成伯克利分校EECS.pptVIP

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MultiValued Logic Synthesis EECS at UC Berkeley多值逻辑合成伯克利分校EECS.ppt

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MultiValued Logic Synthesis EECS at UC Berkeley多值逻辑合成伯克利分校EECS

Testing - Overview Motivation fault models testing methods Automatic Test Pattern Generation (ATPG) algorithms D-algorithm PODEM Socrates SAT Testing: Why? Testing is manufacture verification “Is what I manufactured what I designed?” Incorrect Operation (faults) occurs due to physical defects Logical faults shorts, missing transistors, … Parametric faults process variations, die anomalies, … Faults may be intermittent or permanent Permanent faults may be created during life of the circuit physical/thermal stress radiation Testing: Why? No manufacturing process can guarantee 100% defect free IC’s Larger the circuit, greater the probability of defects occuring Economics: Cost of detecting a faulty component is lowest before it is packaged and embedded in a system and shipped. Detection (either during manufacture or during operation) of intermittent and permanent faults ? reliable circuits Fault Modeling and Testing Logical Fault Single/multiple stuck-at (most used) CMOS stuck-open CMOS stuck-on Bridging faults Parametric faults low/high voltage/current levels gate or path delay faults Parametric (electrical) tests also detect stuck-on faults Logical tests detect stuck-at faults Transition tests detect stuck-open faults Timed transition tests detect delay faults Stuck-at fault test generation To generate a test for y stuck-at 0, we need to find an vector of primary inputs which sets signal y to 1 (justify) and such that some primary output differs between the good circuit and the faulty circuit (propagate) Fault Reductions Dominated fault: If every test for fault f1 detects f2 , then f1 dominates f2 . only have to generate test for f1 Set of faults required for testing is a minimal set with respect to fault equivalence and dominance Fault Reductions Stuck fault checkpoints: [Davidson] [Kohavi, Kohavi] Theorem: In a combinational circuit, any set of tests which detects all single (multiple) stuck faults on all primary inputs and all branches of fanout p