Validating a Modern Microprocessor验证现代微处理器.pptVIP

Validating A Modern Microprocessor Bob Bentley Intel Corporation Enterprise Microprocessor Group Hillsboro, Oregon U.S.A. Moore’s Law - 1965 Moore’s Law - 40 Years Later 300mm Semiconductor Economics Fab $3 billion Pilot line $1-2 billion RD process team $0.5-1 billion The Validation Challenge Microprocessor validation continues to be driven by the economics of Moore’s Law Each new process generation doubles the number of transistors available to microprocessor architects and designers Some of this increase is consumed by larger structures (caches, TLB, etc.), which have no significant impact to validation The rest goes to increased complexity: Out-of-order, speculative execution machines Deeper pipelines New technologies (Hyper-Threading, 64-bit extensions, virtualization, security, … Multi-core designs Increased complexity = increased validation effort and risk Microprocessor Design Microprocessor Design Scope Typical lead CPU design requires: 500+ person design team: logic and circuit design physical design validation and verification design automation 2-2? years from start of RTL development to A0 tapeout 9-12 months from A0 tapeout to production qual (may take longer for workstation/server products) Pentium? 4 Processor RTL coding started: 2H’96 First cluster models released: late ’96 First full-chip model released: Q1’97 RTL coding complete: Q2’98 “All bugs coded for the first time!” RTL under full ECO control: Q2’99 RTL frozen: Q3’99 A-0 tapeout: December ’99 First packaged parts available: January 2000 First samples shipped to customers: Q1’00 Production ship qualification granted: October 2000 RTL – A Moving Target Microprocessor Validation RTL validation environment RTL model is MUCH slower than real silicon A full-chip simulation with checkers runs at ~20 Hz on a Pentium? 4 class machine We use a compute farm containing ~6K CPUs running 24/7 to get tens of billions of simulation cycles per week The sum total of Pentium? 4 RTL simulation cycles run p