姜书艳 数字逻辑设计及应用 18.pptVIP

Chapter 7 Sequential Logic Design Principles( 时序逻辑设计原理 ) Latches and Flip-Flops (锁存器和触发器 ) Clocked Synchronous State-Machine Analysis (同步时序分析) Clocked Synchronous State-Machine Design (同步时序设计) Review of Last Class (内容回顾) 时序逻辑电路 输出取决于输入和过去状态 电路特点：有反馈回路、有记忆元件 双稳态元件 Review of Last Class (内容回顾) 时序逻辑电路 输出取决于输入和过去状态 电路特点：有反馈回路、有记忆元件 双稳态元件 S - R latch（锁存器） S-R Latch with Enable(具有使能端的S-R锁存器) D Latch (D锁存器) Function Description of a D Latch(D锁存器的功能描述) D Latch with CMOS Transmission Gate(利用CMOS传输门的D锁存器) D Latch with CMOS Transmission Gate(利用CMOS传输门的D锁存器) D Latch with CMOS Transmission Gate(利用CMOS传输门的D锁存器) Flip-Flops (触发器) Change its outputs only at the Rising or Falling Edge of a controlling CLK signal. (只在时钟信号的边沿改变其输出状态) Flip-Flops (触发器) 从功能上分 D触发器、S-R触发器、J-K触发器、T触发器 从结构上分 主从结构触发器、边沿触发器 其他类型触发器 带使能端的触发器、扫描触发器 施密特触发器、单稳态触发器 D Flip-Flops (D触发器) Timing Parameters for a D Flip-Flops (D触发器的定时参数) Propagation Delay (传播延迟（CLK?Q）) 第7章作业 7.4(7.2) 7.5(7.3) 7.7(7.5) 7.12(7.9) 7.13(7.10) 7.16(7.13) 7.17(7.14) 7.18(7.15) 7.19(7.16) 7.20(7.19) 7.21(7.20)(c) 7.41(7.27) 7.43(7.28) 7.46(7.34) 7.51(7.47) 7.52(7.49) 7.77(7.68) Draw the Output Waveform of the D Flip-Flop * * * * * * * * * * * * * * * Problem with SR Latch 1 0 1 0 1 0 1 0 Call Cncl S R SR = 01 (undesired glitch) 4 ns Solution: Level-Sensitive SR Latch Add enable input “C” Only let S and R change when C=0 Ensure circuit in front of SR never sets SR=11, except briefly due to path delays Set C=1 after time for S and R to be stable When C becomes 1, the stable S and R value passes through the two AND gates to the SR latch’s S1 R1 inputs. R1 S1 S C R Level-sensitive SR latch Q S C Q Q R Level-sensitive SR latch symbol Solution: Level-Sensitive SR Latch R1 S1 S Call Cncl C Clk R Level-sensitive SR latch Q Glitch on R (or S) doesn’t affect R1 (or (S1) 0 1 0 1 S1 R1 Correct Values when enabled 1 0 1 0 1 0 1 0 Call Cncl S R 1 0 C CLK Positive-Edge Rising-Edge (正边沿 上升沿) Negative-Edge Falling-Edge (负边沿 下降沿) Di