Superscalar Processors.pptVIP

Superscalar Processors 7.1 Introduction 7.2 Parallel decoding 7.3 Superscalar instruction issue 7.4 Shelving 7.5 Register renaming 7.6 Parallel execution 7.7 Preserving the sequential consistency of instruction execution 7.8 Preserving the sequential consistency of exception processing 7.9 Implementation of superscalar CISC processors using a superscalar RISC core 7.10 Case studies of superscalar processors Superscalar Processors vs. VLIW Superscalar Processor: Intro Parallel Issue Parallel Execution {Hardware} Dynamic Instruction Scheduling Currently the predominant class of processors Pentium PowerPC UltraSparc AMD K5- HP PA7100- DEC ? Emergence and spread of superscalar processors Evolution of superscalar processor Specific tasks of superscalar processing Parallel decoding {and Dependencies check} What need to be done Decoding and Pre-decoding Superscalar processors tend to use 2 and sometimes even 3 or more pipeline cycles for decoding and issuing instructions Pre-decoding: shifts a part of the decode task up into loading phase resulting of pre-decoding the instruction class the type of resources required for the execution in some processor (e.g. UltraSparc), branch target addresses calculation as well the results are stored by attaching 4-7 bits + shortens the overall cycle time or reduces the number of cycles needed The principle of perdecoding Number of perdecode bits used Specific tasks of superscalar processing: Issue 7.3 Superscalar instruction issue How and when to send the instruction(s) to EU(s) Issue policies Instruction issue policies of superscalar processors: ---Performance, tread-----? Issue rate {How many instructions/cycle} CISC about 2 RISC: Issue policies: Handing Issue Blockages Issue stopped by True dependency True dependency ? (Blocked: need to wait) Issue order of instructions Aligned vs. unaligned issue Issue policies: Use of Shelving Direct Issue The principle of shelving: Indirect Issue Design space of shelvi