Combined_DS2001.pptVIP

Design Solutions 2001 Custom IC Solutions ASSURA OFFERS... Reduced cost of ownership One tool - one rule file (Interactive and Batch in 1 tool Assura) Capacity and performance for leading edge IC designs For both analog and digital design; patented hierarchical technology that scales with Moore’s law Fast verification cycle times and easy UI Efficient hierarchical debugging environment with a short locator Easy adoption from Diva and Dracula Accurate RC extraction integrated within the verification flow Powerful, practical tools for OPC and Silicon-level verification ASSURA PHYSICAL VERIFICATION EXTRACTION SOLUTIONS PHYSICAL VERIFICATION ROADMAP ASSURA PHYSICAL VERIFICATION EXTRACTION SOLUTIONS ASSURA FEATURES Hierarchical processing with Multiprocessor 64-bit support Powerful debugging capabilities to locate and correct errors quickly view errors hierarchically, easier than viewing all errors flat short locator Fast and efficient full-chip short locator Comprehensive antenna check with robust syntax a must for improving wafer yields ASSURA DRC ENVIRONMENT ASSURA DRC ENVIRONMENT ASSURA FEATURES (cont.) Hypertext error report between layout, schematics or netlist Hierarchical cross probing for blocks, nets, pins, or devices Optimized foundry rule files supported by Cadence Customer training courses Hotline support Master Key license can be used to execute Diva or Dracula jobs Best verification tool for Analog, Digital, RF, SiGe, and SOI designs ASSURA LVS ENVIRONMENT ASSURA LVS ENVIRONMENT ASSURA PHYSICAL VERIFICATION EXTRACTION SOLUTIONS ASSURA PARASITIC EXTRACTION SOLUTION ASSURA RCX HIGHLIGHTS Best-in-class solution for full-chip, device-level parasitic extraction Advanced 3D extraction engine (Bell Labs technology) Superior accuracy High speed and capacity Flexible extraction modes Advanced process technology support Seamless integration into Cadence design environment Preserving the Diva use model Integrated into the DFII environment CONSISTENT