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Design of PLC Timer System Based on FPGALi Kejian, Liu Tong, CaiQizhongSchool of Electronic Information and Control EngGuangxi University of TechnologyLiuzhou Guangxi Chinalijian6262@I26.com; srk04 I26@I26.com;cqiqzh@163. comAbstract-Aiming at the design of the small PLC timer system,based on the analysis of operational characteristics of PLCtimer and the process of PLC user timer program and the datatransmission requirements of PLC user program executionmodule and the timer, a method which applies the FPGAParallel algorithm to designing small PLC timer system , ispresented. The timer system is composed of clock generatorunit, timing unit, timing control unit and the chip select circuit.While the timer runs at the speed of lms timed pulse, theoperation of timer is translated into the operation of RAMmemory cell which is made up of FPGA. That makes user canoperate on RAM memory cell instead of the timer, and it justtake up a few execution time of PLC user program. This paperintroduces the theory and structure of the FPGA timer system,the state transition diagram of timer control module, thetiming diagram of user program execution module operatingon timer, finally take an experiment and gives analysis of theresults.Keywords-PLe timer system;FPGA;dynamic in/ormationcode;paralle/ operation;state transition;1. INTRODUCTIONTimer is an important soft-devices of ProgrammableLogic Controller (PLC) [1 ][2], which is used as the timerelay of relay control system. Timer is widely used inautomatic control system, such as timing sampling, timinginspection, timing scanning, etc. The implementations oftiming are non-programmable hardware timing, softwaretiming and programmable hardware timing. PLC provideshundreds to thousands of timers [3] [4], and their timing unittypically has three kinds like 1 ms, 10ms and lOOms. If thetimer were implemented all by hardware design, it would berelatively simple but would take up a lot of hardwareresources. Therefore, it has great practical sign