Chiprout产品介绍.ppt

Concept High performance System-On-Chip (SOC) for wire-speed routing of IPv4/IPv6 packets between LAN and WAN Architecture LRE = LAN Routing Engine WRE = WAN Routing Engine External Connections DRAM for tables, buffers and CPU RAM FLASH for code, optional SRAM for high speed applications Standard embedded CPU features Technology Advanced low power 0.35m technology Single 3.3 V power supply, 5V tolerant I/O Industrial operating temperature Two packaging options: 160 pin PQFP 176 pin BGA Applications IP Service WAN Access Devices xDSL; Cable Modem; Wireless Local Loop; Satellite; Microwave; CSU/DSU; Cellular Phone (B-CDMA etc.); Smart Payphones; Baseband Modems IP Broadcast/Multicast Tuner IP LAN Modem Card swipes (timekeeping; credit card authorization) JPEG cameras and MPEG streamers Remote telemetry devices Hospital monitoring Async computing devices Block Diagram Operating Modes Hardware Mode IP router block and other hardware resources processing packets in real-time CPU may be running real-time or only background processing in parallel to hardware resources Software Mode All real-time processing performed by CPU Combination of H/W and S/W mode operation Mode determines buffer structure Buffer structure Buffer length 1518 or 1534 bytes (full or ext. Eth. frame) Hardware mode 256 LAN-PWAN/PWAN-LAN buffers (sliding partition) 31 buffers LAN-CPU, 1 buffer CPU-LAN 31 buffers PWAN-CPU, 1 buffer CPU-PWAN 16 buffers SWAN-CPU/CPU-SWAN (sliding partition) Software mode 256 LAN-CPU/PWAN-CPU (sliding partition) 32 buffers CPU-LAN 32 buffers CPU-PWAN 16 buffers SWAN-CPU/CPU-SWAN (sliding partition) Status Header Manager CPU On-chip 32-bit MIPS RISC CPU (standard) Works with standard s/w tools Enable/disable External CPU interface via 16-bit bus or UART On-chip CPU can run system tasks for reduced BOM 8 kB on-chip SRAM Up to 32 MB DRAM and 32 MB FLASH space supported Up to 16 MB SRAM (for fast applications) Glueless external memory connection Interrupt control