Verilog代码(计数器交通灯串并转换).docVIP

1、通用二进制计数器 设计一个二进制计数器（默认为8位计数器），具有加/减计数功能、异步复位、预制数功能。 代码如下： `define WIDTH 8 module BinaryCounter(counter,clk,up_down,load,reset,din); output reg [`WIDTH-1:0] counter; input clk; input up_down; //1为加计数，0为减计数 input reset; input load; //预置数，1有效，din输出到counter input [`WIDTH-1:0] din; always@(posedge clk or posedge reset) begin if(reset) counter=0; else if(load) counter=din; else if(up_down==1) counter=counter+1; else if(up_down==0) begin counter=counter-1; if(counter1) counter=0; end end endmodule 测试程序如下： `define WIDTH 8 module BinaryCounter_tb; reg clk,up_down,reset,load; reg [`WIDTH-1:0] din; wire [`WIDTH-1:0] counter; integer i; initial begin clk=0; reset=1; #5 reset=0; #3000 $stop; end always #5 clk=~clk; /* always@(posedge clk) begin up_down={$random}%2; load={$random}%2; din={$random}%256; end */ initial begin #5; for(i=0;i256;i=i+3) begin din=i; #10; end end initial begin up_down=1; load=1; #20 load=0; #30 load=1; #30 load=0; end always #200 up_down=~up_down; BinaryCounter bcounter(.counter(counter), .clk(clk),.up_down(up_down),.load(load),.reset(reset), .din(din)); endmodule 波形图如下： 图1 二进制计数器波形图 图2 二进制计数器波形图 从图像可看出，20s-50s为加计数，50s-80s时load=1，执行置数功能，80s-200s时up_down=1,为加计数，200s-280s时up_down=0，为减计数。 格雷码计数器 代码如下： `define WIDTH 4 module GrayCounter(gray,clk,rst_n); output [`WIDTH-1:0] gray; input clk; input rst_n; reg [`WIDTH-1:0] binary; always@(posedge clk or negedge rst_n) begin if(!rst_n) binary=0; else if(binary16) begin binary=binary+1; // binary=(binary16)?binary:0; end else binary=0; end assign gray[0]=binary[0]^binary[1]; assign gray[1]=binary[1]^binary[2]; assi