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A Compiler Framework for Mapping Applications to a Coarse-grained Reconfigurable Computer Architecture Girish Venkataramani Walid Najjar University of California Riverside {girish, najjar}@ Fadi Kurdahi Nader Bagherzadeh University of California Irvine {kurdahi, nader}@ Wim Bohm Colorado State University Fort Collins bohm@ bohm@ ABSTRACT The rapid growth of silicon densities has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, in most cases, the application needs to be programmed in hardware description or assembly languages, whereas most application programmers are familiar with the algorithmic programming paradigm. SA-C has been proposed as an expression-oriented language designed to implicitly express data parallel operations. Morphosys is a reconfigurable computer architecture that supports a data-parallel, SIMD computational model. This paper describes a compiler framework to analyze SA- C programs, perform optimizations, and map the application onto the Morphosys architecture. The mapping process involves operation scheduling, resource allocation and binding and register allocation in the context of the Morphosys architecture. The execution times of certain compiled image-processing kernels is comparable to the hand-coded assembly version, and the speed-ups compared to Pentium III range from 3x to 42x. 1. INTRODUCTION Dehon [1] shows that computational density is a strong argument for FPGA-based reconfigurable computing systems over processor-based alternatives for data-parallel applications. However, for applications where the data path is coarse-grained (8 bits or more), the performance and power consumption on FPGAs are handled inefficiently. Also, the compilation time (kernel’s synthesis, placement and routing) for and reconfiguration time on FPGAs are typically long. Coarser grained reconfigurable architectures [2], [15], [16], [17], [18] have been propos