Routing-aware scan chain ordering.pdf

Routing-Aware Scan Chain Ordering Puneet Gupta
, Andrew B. Kahng ?? and Stefanus Mantik ? ECE Department, University of California at San Diego ?? ECE and CSE Departments, University of California at San Diego ? Cadence Design Systems, Inc., San Jose, CA, USA  puneet@, abk@ and smantik@  Abstract Scan chain insertion can have a large impact on routability, wire- length and timing of the design. We present a routing-driven methodology for scan chain ordering with minimum wirelength ob- jective. A routing-based approach to scan chain ordering, while potentially more accurate, can result in TSP (Traveling Salesman Problem) instances which are asymmetric and highly non-metric; this may require a careful choice of solvers. We evaluate our new methodology on recent industry place-and-route blocks with 1200 to 5000 scan cells. We show substantial wirelength reductions for the routing-based flow, versus the traditional placement-based flow: in a number of our test cases, over 86% of scan routing overhead is saved. Even though our experiments are so far timing-oblivious, the routing-based flow does also improve evaluated timing, and practi- cal timing-driven extensions appear feasible. 1 Introduction and Motivation In VLSI design for testability, a scan chain is commonly used to connect the shift registers that store the input and output vectors during the testing phase of manufacturing. Registers in the scan chain are connected as a single path, with ends of the path connected to a primary input (PI) pad and a primary output (PO) pad. Test input values are shifted into the registers through the PI pad; then, a test is performed and the test output values are shifted out through the PO pad. Figure 1 depicts a simple example of a scan chain. SI Q SIQ SI Q O PI I PO FF1 FF2 FF3 Figure 1: Example of a scan chain with three scan registers FF1, FF2, and FF3. In each sequential cell, SI and Q denote the scan- in pin and scan-out pin. PI is the primary input pad and PO is t