051205-Koyanagi.pdf

Different Approaches to 3D Chips Mitsu Koyanagi Dept. of Bioengineering and Robotics, Tohoku University, Japan 1. Introduction 2. Advantages of 3D LSI 3. Progress of 3D Integration Technology 4. 3D Integration Technology of Tohoku University 5. Fabrication and Evaluation 3D LSI Test Chips 6. Applications of Fabricated 3D LSI Chips 7. Summary Outline Cross-Sectional Structure of Super Chip Merits of 3D LSI System LSI Functional Block Sync. Clock Big concerns: Long wiring Global wiring Partition of Functional Blocks Vertical Via Length: （１～50μｍ） [Plan View] Replaced by Vertical Vias No increase of total thickness Present: 2D LSI Future: 3D LSI High Performance Low Power New Functions Low Cost [Cross-Section] 1.0E-02 1.0E+00 1.0E+02 1.0E+04 1.0E+06 1 10 100 1000 Wire length l (gate pich) I n t e r c o n n e c t i o n d e n s i t y f u n c t i o n F ( l ) 1 layer 2 layers 4 layers 9 layers Interconnection Length Distribution in LSIs （Vertical interconnection relative length d=5） 2D-LSI 3D-LSI Estimation of Global Yield ‐ 3D chips give rise to higher global yield. 1 layer stacked 4 layer stacked Chip Size Y i e l d Defect density (pcs/cm2) Available chip number Wafer 8 inch wafer 6 inch wafer Chip Size Chips /wafer A v a i l a b l e c h i p n u m b e r G/W yield Yield Available chip number Chips /wafer Defect density (pcs/cm2)G l o b a l Y i e l d ( % ) Chip Size 00.5 1 1.5 2 10 100 1000 Chip Size (mm2) same process different process 3D Chip Cost 2D Chip Cost Chip Cost versus Chip Size After Dr. Hatada Reduction of Power Consumption by 3D Chip Power of heat provided to heat source: 58.5 mW Temperature at the bottom: 0℃ Distance between heat source and buried interconnection: 31.9μm Micro-bump size : 10μm × 10μm Diameter of buried interconnection: 2.5μm Si thickness : 30μm Maximum temperature difference １．８７℃ Simulated Heat Flow in 3D Structure (a) Contour map of isothermal lines (b) Heat flow distribution 1980 3D SRAM Stacked CMOS