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0_In_CDC_Seminar_2_30NOV06_pdf
Eliminate Clock-Domain Crossing
Errors in RTL with “0-In CDC”
Kevin Edwards
European Product Specialist
0-In CDC Verification
2
Agenda
Introduction
Structural Verification
Protocol Verification
Reconvergence Verification
Coverage and Methodology
Summary and QA
0-In CDC Verification
3
Exploding Complexity
Design Trends from 2000 to 2006*
IC/ASIC Designs Requiring Re-Spins by Type of Flaw
75%
71%
0% 20% 40% 60% 80% 100%
Other
Firmware
IR Drops
Power Consumption
Mixed-Signal Interface
Slow Path
Delays/Glitches
Yield/Reliability
Fast Path
Tuning Analog Circuit
Clocking
Logic/Functional
Percent of Designs Requiring Two or More Silicon Spins
2002 Market Study
2004 Market Study
Design continue to grow, but not
schedules
— Synthesizable gates: 1.1 to 7.0M
— Length of design cycle: 18 to 18 months
Interface complexity expands
— I/O pins: 215 to 380
Reuse is happening
— Percent of reused logic: ~25 to 50%
Speed, and number, of clocks
increases
— Fastest on-chip clock: 200 to 500MHZ
— Number of clock-domains: 5 to 15
* Based on data from the Collett International 2004 FV Survey
0-In CDC Verification
4
Clock-Domain Crossings
Incorrect handling of Clock-Domain Crossing (CDC)
signals is the 2nd major cause of re-spins
Traditional verification techniques do not work for
CDC signals
CDC problems are subtle, will occur in hardware, and
are complex to debug
Mentors 0-In CDC automates CDC
verification, significantly reducing the risk of
CDC related silicon re-spins
t r -I t t
rifi ti , i ifi tl r i t ri f
r l t ili r - i
0-In CDC Verification
5
When an signal between two asynchronous domains violates setup
or hold time, output may go metastable
— Sits at an intermediate voltage then settles “randomly”
Every type of storage element is susceptible to metastability
— Its just a matter of time…
Why Are CDC Signals a Problem
DFF
D
CLK
C
CLK
D
Q
din tff
MTBF
clk ××
=
1
fclk = Clock Frequency
fin = Input Signal Frequency
td = duration of cri
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