Converting Oscillator Phase Noise to Time Jitter.pdf

MT-008 TUTORIAL Converting Oscillator Phase Noise to Time Jitter by Walt Kester INTRODUCTION A low aperture jitter specification of an ADC is critical to achieving high levels of signal-to- noise ratios (SNR). (See References 1, 2, and 3). ADCs are available with aperture jitter specifications as low as 60-fs rms (AD9445 14-bits @ 125 MSPS and AD9446 16-bits @ 100 MSPS). Extremely low jitter sampling clocks must therefore be utilized so that the ADC performance is not degraded, because the total jitter is the root-sum-square of the internal converter aperture jitter and the external sampling clock jitter. However, oscillators used for sampling clock generation are more often specified in terms of phase noise rather than time jitter. The purpose of this discussion is to develop a simple method for converting oscillator phase noise into time jitter. PHASE NOISE DEFINED First, a few definitions are in order. Figure 1 shows a typical output frequency spectrum of a non-ideal oscillator (i.e., one that has jitter in the time domain, corresponding to phase noise in the frequency domain). The spectrum shows the noise power in a 1-Hz bandwidth as a function of frequency. Phase noise is defined as the ratio of the noise in a 1-Hz bandwidth at a specified frequency offset, fm, to the oscillator signal amplitude at frequency fO. PHASE NOISE (dBc/Hz) fo f CLOSE-IN PHASE NOISE BROADBAND PHASE NOISE (LIMITS FREQUENCY RESOLUTION) (REDUCES SNR) 1Hz BW fm Figure 1: Oscillator Power Spectrum Due to Phase Noise Rev.A, 10/08, WK Page 1 of 10 MT-008 The sampling process is basically a multiplication of the sampling clock and the analog input signal. This is multiplication in the time domain, which is equivalent to convolution in the frequency domain. Therefore, the spectrum of the sampling clock oscillator is convolved with the input and shows up on the FFT output of a pure sinewave input signal (see Figure 2). IDEAL ADC ANALOG