Energy savings and speedups from partitioning critical software loops to hardware in embedd.pdf

Energy Savings and Speedups from Partitioning Critical Software Loops to Hardware in Embedded Systems GREG STITT, FRANK VAHID, and SHAWN NEMATBAKHSH University of California, Riverside We present results of extensive hardware/software partitioning experiments on numerous bench- marks. We describe our loop-oriented partitioning methodology for moving critical code from hard- ware to software. Our benchmarks included programs from PowerStone, MediaBench, and Net- Bench. Our experiments included estimated results for partitioning using an 8051 8-bit microcon- troller or a 32-bit MIPS microprocessor for the software, and using on-chip configurable logic or custom application-specific integrated circuit hardware for the hardware. Additional experiments involved actual measurements taken from several physical implementations of hardware/software partitionings on real single-chip microprocessor/configurable-logic devices. We also estimated re- sults assuming voltage scalable processors. We provide performance, energy, and size data for all of the experiments. We found that the benchmarks spent an average of 80% of their execution time in only 3% of their code, amounting to only about 200 bytes of critical code. For various experi- ments, we found that moving critical code to hardware resulted in average speedups of 3 to 5 and average energy savings of 35% to 70%, with average hardware requirements of only 5000 to 10,000 gates. To our knowledge, these experiments represent the most comprehensive hardware/software partitioning study published to date. Categories and Subject Descriptors: C.3 [Special Purpose and Application-Based Systems]: Real-Time and Embedded Systems General Terms: Design, Performance Additional Key Words and Phrases: Hardware/software partitioning, FPGA, synthesis, platforms, low energy, speedup, embedded systems 1. INTRODUCTION Much previous work has shown the advantages of hardware/software parti- tioning in embedded system design. Hardware/software par