Virtex-6 FPGA Memory Interface Solutions Data Sheet.pdf

DS186 (v1.3) April 19, 2010 1 Advance Product Specification ? Copyright 2009–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Introduction The Virtex?-6 FPGA memory interface solutions core provides high-performance connections to DDR3 and DDR2 SDRAMs, QDR II+ SRAM, and RLDRAM II devices. For information about the QDR II+ SRAM, see QDR II+ SRAM, page 4. For information about RLDRAM II devices, see RLDRAM II Memory, page 5. DDR3 and DDR2 SDRAMs This section discusses the features, applications, and functional description of Virtex-6 FPGA memory inter- face solutions in DDR3 and DDR2 SDRAMs. DDR3 SDRAM Features ? 303–533 MHz (600–1066 Mb/s) performance (pending characterization) for center column, single-rank interfaces up to 72 bits wide: ? 400 MHz in a -1 commercial speed grade device ? 533 MHz in a -2 commercial speed grade device ? 533 MHz in a -3 commercial speed grade device ? 303 MHz (606 Mb/s) performance (pending characterization) for dual-rank interfaces up to 72 bits wide ? Hardware validated ? Component support for interface widths up to 144 bits ? Single- and dual-rank UDIMM, SODIMM, and RDIMM support ? 1 Gb density device support (additional densities supported in the MIG tool using the Create Custom Part feature) ? 8-bank support ? x4, x8, and x16 device support ? 4:1 and 8:1 DQ:DQS ratio support ? Configurable data bus widths (multiples of 8, up to 144 bits) ? 4-word, 8-word, and “On the Fly” (OTF) burst support ? Support for 5 to 9 cycles of column-address strobe (CAS) latency (CL) ? On-die termination (ODT) support ? Support for 5 to 8 cycles of CAS write latency (CWL) ? ZQ calibration – initial and periodic (configurable) ? ECC support Virtex-6 FPGA Memory Interface Solutions Data Sheet DS186 (v1.3) April 19, 2010 Advance Product Specification Log