Integrated Delay Analysis of Regulated ATM Switch.pdf

Integrated Delay Analysis of Regulated ATM Switch Joseph Kee-Yin Ng Shibin Song Department of Computing Studies Hong Kong Baptist University Kowloon, Hong Kong Phone: (852)-2339-7864 Fax: (852)-2339-7892 Email : {j ng, ssong } @comp. hkbu .edu. hk ABSTRACT In this paper, we present an efficient and effective method to derive the worst case delay in an ATM switch. In an ATM switch, admitting a hard real-time Connection requires the delays of cells belonging to the connection meeting their deadline without violating the guarantees already provided to connections that are currently active. Previous studies have shown that the real-time connection traffic and the available service can both be described by piece-wise linear jinctions in terms of time. BV utilizing the inverse of the arrival and service functions, we obtain an efficient and effective method to compute the worst case delay of a connection to an ATM switch. We analyze and compare the performance of an ATM switch with priority driven and FIFO scheduling policies under different utilization. We also compare the performance using our proposed “integrated” method with the traditional “independent” method. From simulation experiments, we found out that our method always obtain a higher admission probability and a better estimation of cell delay within an ATM switch. 1. Introduction ATM networks are getting increasingly popular in supporting hard real-time systems/applications. ATM is a connection-oriented packet-switched technology. Before two hosts communicate, a connection must be established between them. A new connection requires a certain quality of service (QOS) and is admitted by the network only if the network can guarantee the requested quality of service without violating the guarantees made to the connections that are currently active. In order to guarantee that the message deadlines are met for each particular connection, we must derive the worst case delay of