Introduction_to_ASIC_verification.pdf

  1. 1、本文档共21页,可阅读全部内容。
  2. 2、原创力文档(book118)网站文档一经付费(服务费),不意味着购买了该文档的版权,仅供个人/单位学习、研究之用,不得用于商业用途,未经授权,严禁复制、发行、汇编、翻译或者网络传播等,侵权必究。
  3. 3、本站所有内容均由合作方或网友上传,本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺!文档内容仅供研究参考,付费前请自行鉴别。如您付费,意味着您自己接受本站规则且自行承担风险,本站不退款、不进行额外附加服务;查看《如何避免下载的几个坑》。如果您已付费下载过本站文档,您可以点击 这里二次下载
  4. 4、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等,请点击“版权申诉”(推荐),也可以打举报电话:400-050-0827(电话支持时间:9:00-18:30)。
查看更多
Introduction_to_ASIC_verification

?2011, Meeta Yadav 1 ASIC Verification Course Overview Fall 2011 Meeta Yadav ?2011, Meeta Yadav 2 Course Overview This course covers the verification process used in validating the functional correctness in todays complex Application Specific Integrated Circuits (ASICs). Topics include fundamentals of simulation based functional verification, stimulus generation, results checking, coverage, debug, and assertions. Provides the students with real world verification problems to allow them to apply what they learn. Instructor Dr. Meeta Yadav Email: myadav@ Office hours: 4:00 to 5:00 Fridays, 3:00 to 4:00 Thursday (DE) TAS TBD Prerequisite ECE 520 ASIC Design or equivalent. A good working knowledge of Verilog or VHDL is essential. This is not suitable as a first course in a hardware description language. ?2011, Meeta Yadav 3 What is ASIC Verification? ?2011, Meeta Yadav 4 Design Complexity Increasing Image Processing Location-Based Services Telematics Broadcasting Computing Communication Entertainment Designs are becoming more complex as more functionality is added to them ?2011, Meeta Yadav 5 Increase in Transistors Per Die Increased functionality increases the number of transistors in the design thus increasing the possibility of error in the design ?2011, Meeta Yadav 6 6 [Collet 2005] Increase in Design Bugs 50% of ASICs require more than one respin 75% of them have logical or functional bugs ?2011, Meeta Yadav 7 7 Solution is: ASIC Verification Functional Verification Formal Verification ?2011, Meeta Yadav 8 ASIC Verification is: 1. Making sure there are no bugs in the design 2. All design functionality has been implemented ?2011, Meeta Yadav 9 What will you learn in this class? To develop a Verification Plan What to Verify? How to Verify it? Develop a reusable testbench Write Assertions Perform Coverage OOP VMM Methodology Think Get close to the bug When am I done? Close the gap ?2011, Meeta Yadav 10 ? Testbench functionality ? Generate stimulus ? App

文档评论(0)

l215322 + 关注
实名认证
内容提供者

该用户很懒,什么也没介绍

1亿VIP精品文档

相关文档