集成电路版图设计规则.docVIP

标题：0.5um 5V (Vgs)/ 40V (Vds) DPTM BCDMOS Process Topological Design Rule  Version #: 0F09  CSMC QRA CONTROLLED Ver#: 0F09 REFERENCE ONLY（FOR FAB1） REVISION UNAVAILABLE 0.5um 5V(VGS)/40V(VDS) DPTM BCDMOS PROCESS Topological DESIGN RULE  Document #: WTD-73D77(1)  1-70  Confidential The information contained herein is the exclusive property of CSMC and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of CSMC.Electronic versions are uncontrolled except when accessed directly from Document Center. Printed versions are uncontrolled except