基于垂直扩散的FPGA温度优化布局算法.pdfVIP

第 29 卷 第 1 期 计算机辅助设计与图形学学报 Vol. 29 No.1 2017 年 1 月 Journal of Computer-Aided Design Computer Graphics Jan. 2017 基于垂直扩散的 FPGA 温度优化布局算法 黄俊英1,2), 林 郁1), 张 超1), 杨海钢1)* 1) (中国科学院电子学研究所可编程芯片与系统研究室 北京 100190) 2) (中国科学院大学 北京 100190) (yanghg@mail.ie.ac.cn) 摘 要: 为减小 FPGA 热梯度的增加对芯片性能和可靠性的影响, 提出一种基于垂直扩散的温度优化布局算法. 首 先, 通过实验分析了芯片温度特性与芯片尺寸之间的关系; 然后, 根据布局后网表计算出过热区域, 利用该区域边 界及扩散系数构建温度优化布局算法, 并引入局部位置调整机制解决逻辑块位置重叠问题. 实验结果表明, 与传统 布局算法的芯片温度相比, 在线长和延时平均仅增加 3.4%和 1.4%的情况下, 该算法的峰值温度平均减小 7.5%, 热梯 度平均减小 20.3%. 关键词: 可编程门阵列; 布局算法; 温度优化; 热梯度 中图法分类号: TP302.1 A Temperature-Aware FPGA Placement Based on Vertical Diffusion Huang Junying1,2), Colin Lin Yu1), Zhang Chao1), and Yang Haigang1)* 1) (System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing 100190) 2) (University of Chinese Academy of Sciences, Beijing 100190) Abstract: In this paper we propose an FPGA placement algorithm for temperature optimization based on vertical diffusion. It aims at reducing the effect of the increase in thermal gradient of FPGA on chip per- formance and reliability. Firstly, we analyzed the relationship between chip size and the temperature and thermal gradient of the chip through experiments. Secondly, according to the placed net list, we computed the hotspot region. Its boundary together with a diffusion coefficient was used to construct the proposed placement algorithm. In addition, we provided an adjustment mechanism of local positions to remove over- laps between logic blocks. Experimental results show a 7.5% and 20.3% reduction on average in peak tem- perature and thermal gradient respectively with a 3.4% and 1.4% increase in wire length and delay, in comparison with their