2004-A clocking technique for FPGA pipelined designs.pdfVIP

Journal of Systems Architecture 50 (2004) 687–696 /locate/sysarc A clocking technique for FPGA pipelined designs Oswaldo Cadenas *, Graham Megson University of Reading, School of Systems Engineering, P.O. Box 225, Whiteknights, Reading RG6 6AY, UK Received 29 July 2003; received in revised form 12 March 2004; accepted 1 April 2004 Available online 2 July 2004 Abstract This paper presents a clocking pipeline technique referred to as a single-pulse pipeline (PP-Pipeline) and applies it to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). A PP-pipeline replicates the operation of asynchronous micropipelined control mechanisms using synchronous-orientated logic resources com- monly found in FPGA devices. Consequently, circuits with an asynchronous-like pipeline operation can be efficiently synthesized using a synchronous design methodology. The technique can be extended to include data-completion circuitry to take advantage of variable data-completion processing time in synchronous pipelined designs. It is also shown that the PP-pipeline reduces the clock tree power consumption of pipelined circuits. These potential applications are demonstrated by post-synthesis simulation of FPGA circuits. 2004 Elsevier B.V. All rights reserved. Keywords: Pipelines; Micropipeline; FPGAs 1. Introduction chronous [11]. Synchronous pipelining uses a simple control based on a global clock signal, Pipelining is a key implementation technique