时序分析教程教程.docxVIP

时序分析术语时序分析的基本模型时序分析是FPGA的重中之重。开始之前请记住时序分析的基本模型为经过寄存器R1的传输延时为经过组合逻辑的传输延时为R2本身的建立时间； （clockslew）为时钟到R1和R2的偏差Launch edge 和 LatchedgeLaunch edge 和 Latchedge分别是时序分析的起点和终点。需要指出的是Latchedge时间=Launch edge时间+期望系统周期时间Data Arrival Time和Data Required Time这两项时间是TimeQuest时序分析的基础，所有的建立时间余量和保持时间余量都是根据这两项时间来决定的。需要注意的是Data Arrival Time和Data Required Time在分析不同的时序节点时，计算的公式有所差别。建立时间余量Clock Setup Slack建立关系是指寄存器R1发送的数据在下一次更新（更换）之前，寄存器R2可用最短时间去锁存数据建立时间余量是指从Launch edge经过一些列延迟数据输出稳定后到Latchedge的长度。Internal Register-to-Register pathsData Arrival Time = Launch Edge + Clock Network Delay to Source Register??tCO+ Register-to-Register DelayData Required Time = Latch Edge + Clock Network Delay to Destination Register – tSU– Setup UncertaintyInput Port to Internal RegisterData Arrival Time = Launch Edge + Clock Network Delay??Input Maximum Delay+ Port-to-Register DelayData Required Time = Latch Edge + Clock Network Delay to Destination Register – tSU– Setup UncertaintyInternal Register to Output PortData Arrival Time = Launch Edge + Clock Network DelayToSource Register??tCO+Register-to-Port DelayData Required Time =LatchEdge + Clock Network Delay to Output Port– Output Maximum DelaytCO指寄存器R1的自身特性tSU指寄存器R2的自身特性如上图所示：Data Arrival Time= 启动沿时间 + Tclk1 + Tco + Tdata= 0ns + 3.2ns + 0.2ns + 0.6ns = 4nsData Required Time = 锁存沿时间 + Tclk2 - Tsu= 10ns + 2ns - 1.4ns = 10.6ns所以：Setup Slack = Data Required Time - Data Arrival Time = 10.6ns - 4ns = 6.6ns保持时间余量Clock Hold Slack保持时间余量是在两个节点（寄存器） 之间，在分析保持关系的过程中“ 到底有多少剩时间可以提供给寄存器用来确保已存数据的稳定”。由于保持时间余量是指当前Latch edge和下一个Launch edge的距离。所以上面公式可以写成：Internal Register-to-Register pathsData Arrival Time = Launch Edge + Clock Network Delay to Source Register??tCO+ Register-to-Register DelayData Required Time = Latch Edge + Clock Network Delay to Destination Register+tH +Hold UncertaintyInput Port to Internal RegisterData Arrival Time = Launch Edge + Clock Network Delay??Input Maximum Delay+ Port-to-Register DelayData Required Time = Latch Edge + Clock Network Delay to Destination