ElectricalStressDegradationofSmall-GrainPolysiliconThin.pdfVIP

Electrical Stress Degradation of Small-Grain Polysilicon Thin-Film Transistors Domenico Palumbo, Silvia Masala, Paolo Tassini, Alfredo Rubino, and Dario della Sala Copyright © 2007 IEEE. Reprinted from IEEE Transactions on Electron Devices, VOL 54, NO 3, March 2007. Abstract—This paper is focused on the stability of n- the threshold voltage spreading [4], avoiding more com- channel laser-crystallized polysilicon thin-fi lm transis- plicated pixel circuit to overcome this problem [5], [6] and tors (TFTs) submitted to a hydrogenation process during obtaining brightness uniformity over large areas. the fabrication and with small grains dimension.With Their drawback is the instability after electrical stress [7], the aid of numerical simulations, we investigate the ef- [8], due to a high density of in-grain and grain boundary fects of static stress using two types of procedures: the defects, to poor properties of the gate insulator and to on stress and the hot carrier stress. Results show that the poor polysilicon/ oxide interface [9]. variations of trap state density into the whole polysilicon layer and not only near the drain junction are responsi- The purpose of this paper is to understand which are the ble for the degradation of TFTs performances in both the main mechanisms originating from device degradati