Reduced Voltage Scaling in Clock Distribution Networks 外文参考文献.docVIP

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Reduced Voltage Scaling in Clock Distribution Networks 外文参考文献.doc

Reduced Voltage Scaling in Clock Distribution Networks 外文参考文献

HindawiPublishingCorporation VLSIDesign Volume2009,ArticleID679853,7pages doi:10.1155/2009/679853 ResearchArticle ReducedVoltageScalinginClockDistributionNetworks KhaderMohammad,AymanDodin,BaoLiu,andSosAgaian DepartmentofElectricalandComputerEngineering,UniversityofTexasatSanAntonio,SanAntonio,TX78249,USA CorrespondenceshouldbeaddressedtoKhaderMohammad,hajkhader@ Received28April2009;Accepted18December2009 RecommendedbyXianlongLongHong Weproposeanovelcircuittechniquetogenerateareducedvoltageswing(RVS)signalsforactivepowerreductiononmainbuses andclocks.Thisisachievedwithoutperformancedegradati

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