Synopsys实验系列4编译与优化DesignCompiler.pptx

Synopsys 实验系列4_编译与优化_Design Compiler;Company Logo;What do WE Mean by “Synthesis”?;Design Compiler ( DC ) 简介;Design Compiler Flow;Basic Synthesis Flow;Synthesis Transformations;Synthesis Transformations;Synthesis Is Constraint-Driven;Three Interfaces to Design Compiler;2 Setting Up and Saving Designs;Unit 2 Objectives;Setting Up and Saving Designs in Flow;;2-1 启动DC and 读RTL代码;2-2 层次化的 RTL Designs;Company Logo;※ 2-4 Reading .ddc Design Files;※ 2-5 Alternative Commands for Reading RTL;;;2-6 需要指定的库：;2-7 compile需要指定target_library;※ 2-8 工艺库的内部描述;2-9 设置Target Library ;在DC中许多命令都会首先‘auto-link