时间交织ADc.pdf

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时间交织ADc

Bibliography [1] A.M. Abo, Design for reliability of low-voltage, switched-capacity circuits. Ph.D. Thesis, University of California, Berkeley, 1999 [2] A.M. Abo, P.R. Gray, A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J. Solid-State Circuits 34(5), 599–606 (1999) [3] B.K. Ahuja, An improved frequency compensation technique for CMOS operational ampli- fiers. IEEE J. Solid-State Circuits 18(6), 629–633 (1983) [4] V.J. Arkesteijn, Analog front-ends for software-defined radio receivers. Ph.D. dissertation, University of Twente, 2007 [5] V.J. Arkesteijn, E.A.M. Klumperink, B. Nauta, Jitter requirements of the sampling clock in software radio receivers. IEEE Trans. Circuits Syst. (TCAS) II 53(2), 90–94 (2006) [6] C.W. Barbour, Simplified PCM analog to digital converter using capacity charge transfer, in Proc. of the Telemetering Conf. (1971), pp. 4.1–4.11 [7] A. Barna, D.I. Porat, Integrated Circuits in Digital Electronics (Wiley, New York, 1973), pp. 353–354 [8] W.C. Black, D.A. Hodges, Time interleaved converter arrays. IEEE J. Solid-State Circuits 15(6), 1022–1029 (1980) [9] M. Boulemnakher, E. Andre, J. Roux, F. Paillardet, A 1.2 V 4.5 mW 10 b 100 MS/s pipelined ADC in 65 nm CMOS, in ISSCC Dig. Tech. Papers (2008), pp. 250–251 [10] T.B. Cho, P.R. Gray, A 10 b, 20 Msample/s, 35 mW pipeline A/D converter. IEEE J. Solid- State Circuits 30(3), 166–172 (1995) [11] R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideovt, E. Bassous, A.R. LeBlanc, Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J. Solid-State Circuits 256–268 (1974) [12] S. Devarajan, L. Singer, D. Kelly, S. Decker, A. Kamath, P. Wilkins, A 16 b 125 MS/s 385 mW 78.7 dB SNR CMOS pipeline ADC, in ISSCC Dig. Tech. Papers (2009), pp. 86–87 [13] A.G.F. Dingwall, Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converter. I

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