Si5351芯片资料.pdf

AN554 Si5350/51 PCB LAYOUT G UIDE 1. Introduction The Si5350/51 Any-Frequency Octal CMOS Clock Generator + VCXO are the industrys most frequency flexible, lowest power, lowest jitter programmable clocks targeting cost-sensitive consumer, enterprise and communications applications. The devices can synthesize combinations of 8 unique, non-integer related frequencies up to 160 MHz with 0 ppm frequency error, providing greater frequency flexibility than competing solutions. The Si5350/51 simultaneously generates free-running and synchronous clocks, making it ideal for replacing multiple clock ICs, XOs and VCXOs with a single device. Because the Si5350/51 consolidates clocking to a central location, it is necessary to consider the layout implications. This application note provides layout guidance to ease PCB development with centralized clocking. 2. Topologies Several layout strategies can be employed when routing CMOS (single-ended) signals. The most common technique is a simple point-to-point connection, but other techniques involve fanout (point-to-multi-point). All topologies rely upon transmission lines (lines long enough, electrically, to have delay from source to receiver). 3. Transmission Lines For optimized clock signal routing, clock signals should be kept relatively short or treated as transmission lines for longer distances. The connection is considered a transmission line when the line length measured in delay (seconds) is close to the 20–80% rise/fall time of the clock signal. Lines shorter than this metric will settle quickly with little overshoot or undershoot. For the Si5350/51, it is recommended to treat clock signals as transmission lines if the trace distance is greater than 5 cm. As shown