基于FPGA高速FIR数字滤波器设计.PDFVIP

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  • 2017-06-04 发布于湖北
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基于FPGA的高速FIR数字滤波器的设计 王心焕 (浙江大学信息工程学院 浙江杭州 310029) 验证,在ISE软件上进行了功能仿真、时序仿真和综合,并给出了综合的电路框图、资源使用情况以及最高工作频率。通过 运用多种优秀的快速算法及流水线技术,可以打破FPGA中缺乏实现乘累加运算有效结构的缺点,实现高速FIR数字滤波 器的设计,使FPGA在数字信号处理方面有长足发展。 关键词:分布式算法;Booth算法;Wallace树;超前进位加法器;进位选择加法器;流水线技术;ISE 中图分类号:TN713 文献标识码:B 文章编号:1004—373X(2007)15—184—04 FIR Filter BasedonFPGA HighSpeedDigitalDesign WANGxinhuan (CollegeofInformationScienceandEngineering,ZhejiangUniversity,Hangzhou,310029,China) distributed treeand adder,as Abstract:Usingalgorithm,Boothalgorithm,Wallacecarry—look—aheadadder,carry—select wellas FIR filter basedonFPGAis takea pipeliningtechnology,ahighspeeddigitaldesign presented.Let’Slow—passdigital FIR for is filter functionalsimula— filter verificationofthe done Matlab example.The spectrumbyUsing auxiliarydesign,the on the circuit useofresourcesandthe simulationand is ISE,and schematic tion,timing synthesisapplied general diagram,the maximum are theuseofa ofexcellentandfast operatingfrequencygiven.Through variety algorithmpipeline ofeffectivestructureforrealizationofcumulative inFPGA,canbe FIR king operation,theshortcomings broken,highspeed filter canbeachieved,andFPGAinthefieldof canbe andbounds. digitaldesign digitalsignalprocessingdevelopedbyleaps Keywords:distributedalgorithm;Boothalgorithm;Wallacetree;carry—look—aheadadder;carry—select technology;ISE

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