第八章综合与STA.pptVIP

第八章 综合策略及静态时序分析 Outlines Logic Synthesis Compiling Strategy Physical Synthesis Compiling Strategy Synthesis Using Synopsys’s Design Compiler (DC) Static Timing Analysis (STA) STA Using Synopsys’s Primetime (PT) Statistical Static Timing Analysis (SSTA) What Logic Synthesis Do? Selecting and Using a Compiling Strategy Compiling Strategy: Top-down The top-level design and all its sub design are compiled together Advantages: Only top level constraints are needed Better results due to optimization across entire design Disadvantages Long compile times Incremental changes to the sub-blocks req